The present invention relates to fabrication of integrated circuits, and more particularly to fabrication of dielectric in trenches formed in a semiconductor substrate for a nonvolatile memory.
Dielectric-filled trenches in a semiconductor substrate have been used to provide isolation between active areas of an integrated circuit. The active areas contain circuit elements such as transistor regions, interconnect lines, etc. FIG. 1 illustrates fabrication of the dielectric-filled trenches in a monocrystalline silicon substrate 110. Silicon dioxide layer 120 (xe2x80x9cpad oxidexe2x80x9d) is grown on substrate 110. Silicon nitride 130 is deposited on oxide 120. A photoresist mask (not shown) is photolithographically formed on nitride 130 to define trenches 140. Nitride 130, oxide 120 and substrate 110 are etched through the mask openings. Trenches 140 are formed in substrate 110 as a result.
A thick silicon dioxide layer 150 is formed over the structure. Oxide 150 fills the trenches 140 and covers the nitride 130. Oxide 150 is polished using a chemical mechanical polishing process (CMP) that stops on nitride 130. The resulting structure is shown in FIG. 2. Then nitride 130 and oxide 120 are removed (FIG. 3). The thickness of trench oxide 150 may be reduced by an etch at this stage if desired.
FIGS. 4-5 illustrate a modified trench fabrication process for a flash memory. Silicon dioxide 120 is formed on substrate 110. Oxide 120 will be used as a tunnel oxide for the flash memory cells. Conductive polysilicon 410 is deposited on oxide 120. Polysilicon 410 will be used to fabricate floating gates for the memory cells. Then silicon nitride 130 is deposited. A photoresist mask (not shown) is photolithographically formed on nitride 130 to define isolation trenches 140. Nitride 130, polysilicon 410, oxide 120, and substrate 110 are etched through the mask openings. Trenches 140 are formed as a result. Polysilicon 410 is thus self-aligned to the trenches. Then silicon dioxide 150 is deposited as in FIG. 1, and polished by a CMP process that stops on nitride 130. See FIG. 5, and see K. Shimizu et al., xe2x80x9cA Novel High-Density 5F2 NAND STI Cell Technology Suitable for 256 Mbit and 1 Gbit Flash Memoriesxe2x80x9d, IEDM Technical Digest, 1997, pages 271-274. Silicon nitride 130 is later removed.
It is desirable to reduce the thickness to which the oxide 150 is deposited because the reduced oxide thickness will result in reduced oxide deposition and polishing times.
The invention is defined by the appended claims which are incorporated into this section by reference. Summarized below are some features of the invention.
In the structure of FIG. 3, the top surface 150T of oxide 150 must not be allowed to fall below the top surface of silicon substrate 110. If the top surface 150T of oxide 150 falls below the top surface of substrate 110, then some conductive material formed later during fabrication could be caught up in the trench above the oxide 150, and could reduce the resistance of the parasitic transistor in the trench area. To ensure that the top surface of oxide 150 does not fall below the top surface of substrate 110, oxide 150 is deposited to a large thickness. At the stage of FIG. 1, the top surface of oxide 150 lies above the top surface of nitride 130 in the trench areas.
The same holds true for FIG. 4.
The inventor has observed that due to the presence of polysilicon 410 in the structure of FIG. 4, there is a wider margin of error with respect to the thickness of oxide 150 when oxide 150 is deposited. The top surface 150T of oxide 150 can be located below the top surface of nitride 130, as shown in FIG. 6, because the top surface of nitride 130 is positioned higher above substrate 110 due to the presence of polysilicon 410.
Other embodiments and variations are described below. The invention is defined by the appended claims.